`include "defines.v"
`timescale 1ns / 1ps

module log(
    input  wire                  cpu_clk_50M,
    input  wire                  cpu_rst_n,
    input wire[`REG_BUS] inst
    );
reg [31:0]  count;
reg [`REG_BUS] inst_save;
reg  good;
reg  bad;

always @(posedge cpu_clk_50M) begin
    if(cpu_rst_n == `RST_ENABLE) begin
        count <= 0;
        inst_save <= 0;
        good <= 0;
        bad <= 0;
    end
    else begin
        case (inst)
            `LOG_INST: begin
                count <= count + 1;
            end 
            `BAD_INST: begin
                bad <= 1;
            end
            `GOOD_INST: begin
                good <= 1;
            end
            default: begin
            end
        endcase
    end
end

endmodule